INVESTIGADORES
LIPOVETZKY Jose
artículos
Título:
Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects
Autor/es:
JULIANO BENFICA, BRUNO GREEN, LETÍCIA BOLZANI POEHLS, FABIAN VARGAS, NILBERTO H. MEDINA, NEMITALA ADDED, VITOR A. P. DE AGUIAR, EDUARDO L. A. MACCHIONE, ; FERNANDO AGUIRRE, MARCILEI A. G. SILVEIRA, MARTÍN PEREZ, MIGUEL SOFO HARO, IVAN SIDELNIK, JERÓNIMO BLOSTEIN, JOSÉ LIPOVETZKY, EDUARDO A. BEZERRA.; MARTÍN PEREZ, MIGUEL SOFO HARO, IVAN SIDELNIK, JERÓNIMO BLOSTEIN, JOSÉ LIPOVETZKY, EDUARDO A. BEZERRA.; JOSÉ LIPOVETZKY; EDUARDO A. BEZERRA
Revista:
IEEE TRANSACTIONS ON NUCLEAR SCIENCE
Editorial:
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Referencias:
Lugar: New York; Año: 2016 vol. 64 p. 1294 - 1300
ISSN:
0018-9499
Resumen:
his work proposes a novel methodology to evaluateSRAM-based FPGA?s susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, Total-Ionizing Dose (TID) and TID-imprinted effect on BlockRAM cells.The proposed procedure is demonstrated for SEU measurementson a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletronaccelerator for the SEU test with heavy-ions, whereas TID wasdeposited by means of a Shimadzu XRD-7000 X-ray diffractome-ter. In order to observe the TID-induced imprint effect inside theBlockRAM cells, a second SEU test with neutrons was performedwith Americium/Beryllium (241 AmBe). The noise was injectedinto the power supply bus according to the IEC 61.000-4-29 stan-dard and consisted of voltage dips with 16.67% and 25% of theFPGA?s VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given inerror/bit.day, is calculated for the FPGA?s BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.