A 180 nm CMOS temperature-compensated voltage reference with multiple outputs

CASSANI, M.; GOYRET, JUAN; CARBONETTO, S.; GARCÍA INZA, M.A.

San Juan

Congreso; IEEE Biennial Congress of Argentina (ARGENCON); 2022

Universidad Nacional de San Juan

A low power voltage reference with low temperature dependence and multiple outputs is designed and simulated in a CMOS 180 nm process. This circuit is required by the transducer of a gas sensor project planned to be integrated in the same chip. The design is divided in two main parts. One, is a self-biased single output voltage reference with a temperature coefficient of 27ppm/°C obtained by compensating opposite thermal coefficients in the circuit. Employing Montecarlo’s method, the estimated mean value is 828.49mV with standard deviation of 11.25mV at room temperature. Line sensitivity is 0.51%/V from 0.94V to 1.80V and total noise is 180µV RMS . The second part is a circuit that allows generating auxiliary voltages with specifically required values of 0.55V and 1.10V for different stages of the transducer. Total noise for each of these signals are 202µV RMS and 382µV RMS . Total power consumption is about 485nW.