INVESTIGADORES
FINOCHIETTO jorge Manuel
congresos y reuniones científicas
Título:
Design and Implementation of Packet Switching Capabilities on 10GbE MAC Core
Autor/es:
R. ARENAS, J. M. FINOCHIETTO, L. ROCHA
Lugar:
Ipojuca, Brazil
Reunión:
Conferencia; VI Southern Programmable Logic Conference; 2010
Resumen:
This paper proposes the integration of packet switching capabilities to
10 Gigabit Ethernet (10GbE) Medium Access Control (MAC) devices. For
this purpose, the architecture of a MAC core is first analyzed to
evaluate where these capabilities can be best placed. Next, a general
packet switching architecture is proposed which comprises
classification, queueing and scheduling stages. The proposed
classification stage exploits the intrinsic latency of the MAC
processing to simultaneously inspect the packet header and determine
the destination queue where the packet is to be stored. The proposed
architecture was implemented and integrated inside a 10GbE MAC core,
and validated on a FPGA development board. The main contribution of
this work is the analysis, design and verification of an advance MAC
core implementation which integrates switching capabilities. This
architecture is evaluated in terms of resource usage and scalability.