Performance Evaluation of Packet Classification on FPGA-based TCAM Emulation Architectures

CARLOS ZERBINI; JORGE M. FINOCHIETTO

Anaheim

Conferencia; IEEE Globecom 2012; 2012

IEEE

Packet classification techniques are continuously challenged as network bandwidth increases and new services are deployed. Ternary Content Addressable Memories (TCAMs) have traditionally been used for scenarios requiring high-speed packet processing. However, TCAM-based classification suffers from high power consumption and clock rate limitations. Among several proposed solutions, TCAM emulation through RAM has emerged as a more flexible and energy-efficient strategy. On the other hand, Field-Programmable Gate Array (FPGA) devices have been evolving providing not only abundant logical resources but also an increasing number of integrated RAM blocks. This paper investigates performance and trade-offs related to TCAM emulation in FPGAs. In particular, we analyze the impact of encoding different key ranges on rules for different configurations in terms of the search key length and the number of rules. To validate and evaluate actual performance, we report and discuss results of real implementations on FPGA devices. Our work shows that classification rates above 300Mpps for both large keys and rule sets can be implemented with only a few megabits of RAM when considering up to medium size range matching intervals.