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Título:
Timing Synchronization and Viterbi Decoding for FPGA-based SDR Platforms
Autor/es:
MARTÍN AYARDE; GABRIEL TAMAGNONE; GRACIELA CORRAL BRIONES
Lugar:
Bahía Blanca
Reunión:
Workshop; 2019 XVIII Workshop on Information Processing and Control (RPIC); 2019
Institución organizadora:
RPIC
Resumen:
Abstract:In this paper we analyze the integration of a digital clock and data recovery with a Viterbi decoder and propose a new interface module that minimizes the detrimental effects of clock jitter on decoded data. The proposed interface avoids decoder idle times and the utilization of a faster clock, optimizing the power consumption. A detailed performance analysis shows that jitter effects on decoding data can be practically eliminate with an appropriate design of the proposed interface.
