A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems

GIANNI, P. CARRER, H.S. CORRAL BRIONES, G. HUEDA, M.R.

Córdoba

Conferencia; VII Southern Conference on Programmable Logic (SPL), 2011; 2011

Universidad Nacional de Córdoba

This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the parallel processing implementation in the feedback loop of traditional DPLLs. Numerical results show that the bandwidth and the capture range of the new parallel DPLL are close to those achieved by a serial DPLL. This excellent behavior makes the proposed low latency parallel DPLL architecture an excellent choice for implementing high speed CR systems in both ASIC and FPGA platforms.