A Soft-Error Resilient Route Computation Unit for 3D Networks-on-Chips

A. COELHO; CHARIF, A.; N. ZERGAINOH; FRAIRE, J. A.; R. VELAZCO

Dresden

Conferencia; Design Automation and Test in Europe Conference (DATE); 2018

Three-dimensional Networks-on-Chips (3D-NoCs)have emerged as an alternative to further enhance the performance,functionality, and packaging density of 2D-NoCs.However, the increasing complexity of NoC routers, the continuousminiaturization of silicon technology, the lower operatingvoltages and higher frequencies have made the NoC increasinglyvulnerable to soft errors. In particular, transient faults occurringin the route computation unit (RCU) can provoke misroutingwhich may lead to severe effects such as deadlocks or packetloss, corrupting the operation of the entire chip. By combininga reliable fault detection circuit leveraging circuit-level doublesampling,with a cost-effective rerouting mechanism, we develop afull fault-tolerance solution that can efficiently detect and correctsuch fatal errors before the affected packets leave the router.To validate the proposed solution, we also introduce a novelmethod for simulation-based fault-injection based on the NoC?sgate-level netlist. Experimental results obtained from a partiallyand vertically connected 3D-NoC indicate that our solution canprovide a high level of reliability in the presence of errors, atthe expense of an area and power overhead of 4.1% and 6.8%respectively.