Noise analysis of MIDNA Skipper-CCD readout ASIC

F. ALCALDE; T. ENGLAND; H. SUN; D. BRAGA; M. SOFO HARO; J. LIPOVETZKY; J. ESTRADA; F. FAHIM

Conferencia; 2023 Argentine Conference on Electronics (CAE); 2023

The MIDNA ASIC is an integrated circuit that implements the analog signal processing blocks needed for reading Skipper Charge-Coupled Devices (CCD). The ASIC has four parallel readout channels, each one comprised by a preamplifier, a DC restore, a buffer and an integrator stage, that provide signal amplification and which perform analog correlated double sampling. MIDNA output is a signal proportional to the amount of charge present in the floating gate node of the CCD and it is digitized by the acquisition system. An analysis of the noise produced by the signal-processing stages of the ASIC and their impact on the output noise is presented. The conclusion is that the integrator operational amplifier low-frequency noise is the most relevant issue for an acquisition and averaging of a large number of samples.