Savitzky-Golay Filter design in FPGA described in VHDL

ROCCO, L.; DE MICCO, L.; GAYOSO, C. A.

Buenos Aires

Congreso; Congreso Argentino de Sistemas Embebidos CASE2015; 2015

The present work consists in the implementation of Savitzky-Golay filters described in VHDL (VHSIC Hardware Description Language). The work includes a complete system able to design and test the filters. In the case of the design, an application that generates the parametric IP Cores of the filter was developed. The application allows the user to select the desired parameters of the filter and automatically generates the filter?s VHDL code. This file is ready to be compiled and programmed in any FPGA (Field Programmable Gate Array) with minimum hardware requirements. The testing issue was resolved by a circuit board that was designed and implemented, customized for this case. The board is in charge of solving the inputs and outputs of the FPGA, this is, the analog to digital and digital to analog conversions. The board is also able to add noise to the incoming signal before being digitalized, it also has a clock generator circuit and digital isolators to protect the FPGA against harmful voltages. This platform allows designing and testing the filter in order to implement it in an ASIC (Application-Specific Integrated Circuit).