Middleton Class A Noise Median Estimator: FPGA and Software Implementation

RABIOGLIO, L. A.; CEBEDIO, M. C.; ARNONE, L.; DE MICCO, L.; MOREIRA, J. CASTIÑEIRA

IEEE Embedded Systems Letters

IEEE

Año: 2024 p. 1 - 1

1943-0663

This paper focuses on the FPGA (Field-Programmable Gate Array) implementation of a Class A Middleton noise estimator, aiming to enhance its efficiency and performance. The inherent algorithm of the estimator undergoes strategic enhancements, leveraging median approximations. This endeavor leads to the development of a more streamlined and expeditious architecture. The research not only introduces the refined architecture but also conducts a comparative analysis of its attributes. The outcomes of this investigation show the benefits of algorithmic optimization, as the execution times achieved in hardware significantly surpass those attainable through software-based implementation. This underscores the practicality of the algorithmic refinement and also the notable advantages of the FPGA-based execution in terms of computational speed.