Hardware implementation of improved processing architectures for complementary sets of four sequences

DONATO, P. G.; FUNES, M.; HADAD, M.; MAESTRI, S.

Santa Fe

Congreso; 37th JAIIO – 9th Argentine Symposium on Computing Technology (AST 2008); 2008

SADIO - Sociedad Argentina de Informatica

Complementary sets of sequences  are  currently being  applied to multiple fields  of engineering. Their  particular mathematical  properties make them very useful in a wide range of aplications (communications, robotics, etc) and allow  to  implement them  in programmable logic devices (e.g.  FPGA). Efficient architectures that  reduce the computational load has been used  in the most of  the applications proposed in the literature.  This paper describes improved generator and correlator architectures for complementary sets of four sequences,  in order to obtain lower hardware requirements  for  their implementation in FPGAs.