IIIE 20352
INSTITUTO DE INVESTIGACIONES EN INGENIERIA ELECTRICA "ALFREDO DESAGES"
Unidad Ejecutora - UE
congresos y reuniones científicas
Título:
Design and Evaluation of an All-Digital Programmable Delay Line in 130-nm CMOS
Autor/es:
PABLO S. MANDOLESI; FERNANDO CHIERCHIE; JUAN I. MORALES; EDUARDO E. PAOLINI
Lugar:
Bahía Blanca, Buenos Aires
Reunión:
Congreso; XVIII Reunión de trabajo en Procesamiento de la Información y Control; 2019
Institución organizadora:
Universidad Nacional del Sur
Resumen:
Programmable delay lines are often used to provide precise transition timing control in very-large-scale integration (VLSI) systems. In this work, a digitally controlled delay linethat achieves a resolution step of 340 ps and a maximum delay of 50 ns is proposed. The delay element has a linear delay characteristic and calibration capabilities in a range of 20% usinga mixed model of current starving and load switching strategy. Experimental results of the circuit implementation in a 130-nm CMOS process are presented.
