Hardware Co-Processing Unit for Real Time Scheduling Analisys

J. URRIZA; R. CAYSSIALS; E. FERRO

Ipojuca, Brazil

Conferencia; VI IEEE Southern Conference on Programmable Logic DF; 2010

IEEE

In this paper we describe the design and the implementation of a co-processing unit for real-time scheduling analysis. This unit implements an arithmetic architecture that determines the schedulability of a fixed-priority discipline without requiring processing time from the system processor. Fixed-priority discipline is one of the most important disciplines in real-time. In this discipline, a priority is assigned to each task and it remains fixed during runtime. Exact schedulability conditions are useful to determine if the real-time requirements can be met. However, when the schedulability is required to be determined during runtime, the complexity of the calculus requires so much processing time that makes the system unfeasible. The processing unit implements efficiently the real-time analysis of a set of real-time tasks scheduled under a fixed-priority discipline and can be used in different real-time areas.