IIIE 20352
INSTITUTO DE INVESTIGACIONES EN INGENIERIA ELECTRICA "ALFREDO DESAGES"
Unidad Ejecutora - UE
congresos y reuniones científicas
Título:
VLSI Microprocessor Architecture for a Simplicial PWL Function Evaluation Core
Autor/es:
J. A. RODRIGUEZ, V. M. JIMENEZ FERNANDEZ, P. JULIÁN, O. AGAMENNONI, O. LIFSCHITZ
Lugar:
Buenos Aires, Argentina
Reunión:
Conferencia; 3ra. Escuela Argentina de Microelectrónica, Tecnología y Aplicaciones; 2008
Institución organizadora:
INTI-CONEA
Resumen:
In this paper, we present the VLSI design for a piecewise linear (PWL) function evaluator. This design, is based on a dedicated microprocessor architecture which lets reprogramability not only in the function, but also in the dimension (n = 1, · · · , 6). It was developed by using industry electronic design automation (EDA) tools and a standard CMOS 0.5 µm technology. Logic and analog simulations show the correct operation of the design.
