IIIE 20352
INSTITUTO DE INVESTIGACIONES EN INGENIERIA ELECTRICA "ALFREDO DESAGES"
Unidad Ejecutora - UE
artículos
Título:
A low power integrated circuit for interaural time delay estimation without delay lines
Autor/es:
A. CHACON-RODRIGUEZ, F. MARTIN-PIRCHIO, S. SANUDO, P. JULIAN
Revista:
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
Editorial:
IEEE
Referencias:
Lugar: New York; Año: 2009 vol. 56 p. 575 - 579
ISSN:
1057-7130
Resumen:
A low power integrated circuit (IC) for estimation of the delay between two infinite clipped (digital) signals is designed and implemented in a 0.35m technology. The proposed circuit is based on a sliding mode control system, and avoids the use of delay lines, which reduces significantly the power consumption. The IC is intended to work in ultra low power sensor network nodes performing localization in the audio range [20, 1000] Hz, as part of an environmental protection network in a forest. Power dissipation results show a core power consumption of 1.04W at 3.3V, and only 282nW at 1.8V in both cases with a clock frequency of 200kHz. Circuit is fully operative and was successfully tested on field as a part of a low power bearing sensor unit.
