IIIE 20352
INSTITUTO DE INVESTIGACIONES EN INGENIERIA ELECTRICA "ALFREDO DESAGES"
Unidad Ejecutora - UE
artículos
Título:
Post-silicon Validation Procedure for a PWL ASIC Microprocessor Architecture
Autor/es:
O. LIFSCHITZ, J. A. RODRÍGUEZ, P. JULIÁN, AND O. AGAMENNONI
Revista:
IEEE LATIN AMERICA TRANSACTIONS
Editorial:
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Referencias:
Lugar: Sao Paulo; Año: 2011 vol. 9 p. 492 - 497
ISSN:
1548-0992
Resumen:
In this paper, we present the environment set for validation and testing a particular ASIC that implements a piecewise linear (PWL) architecture. Description for a package debug propose is included. Methodologies for power consumption and maximum operation frequency estimation, based on laboratory measurements, are described.
