A CACHE MISS ANALYSIS FOR MULTITHREADED ARCHITECTURES

JOSÉ LUIS HAMKALO; AUGUSTO VEGA; BRUNO CERNUSCHI FRÍAS

Orlando, Florida, USA, Noviembre 2008.

Congreso; 20th IASTED International Conference on Parallel and Distributed Computing and Systems "PDCS 2008", Orlando, Florida, EEUU. 16 al 18 de noviembre de 2008, pp. 467-472,; 2008

IASTED

A new model for cache misses classification in a multithreadingenvironment is given. This model is called the “D4C” model. The D4C model discriminates conflict misses in closed conflicts (a thread with himself) and crossed conflicts (conflicts between threads or interferences). SWSA-MT, 2 and 4 way set associative cachememories organizations are analyzed for multithreading processing. The results obtained from the execution of the SPLASH-2 benchmarks, show that the SWSA-MT and 4WSA organizations have similar performance. It is observed that the SWSA-MT scheme shows a better crossedconflictmiss rate relative to the other studied schemes. This is an important characteristic for the SWSA-MT organization and it is due to the private memories that minimize the destructive interference between the threads.