A Low-Power Integrated Circuit for Interaural Time Delay Estimation Without Delay Lines

CHACON-RODRIGUEZ, A.; MARTIN-PIRCHIO, F.; SAÑUDO, S.; JULIÁN, P.

IEEE

Otro; IEEE Transactions, Circuits and Systems ? II: Brief Papers; 2009

A low-power IC for the estimation of the delay between two infinitely clipped (digital) signals is designed and implemented in a 0.35-mum standard CMOS technology. The proposed circuit is based on a sliding-mode control system and does not need past values of the inputs, which are usually stored using chains of digital registers or analog delay lines and significantly increase the power consumption. The IC is intended to work in ultralow-power miniature sensor network nodes performing localization in the audio range [20, 1000] Hz, as part of a forest environmental protection network. Power dissipation results show a core power consumption of 1.04 muW at 3.3 V and only 282 nW at 1.8 V-in both cases with a clock frequency of 200 kHz. The circuit is fully operative and was successfully tested on field as part of a low-power bearing sensor unit.