INVESTIGADORES
BONETTO Fabian Jose
congresos y reuniones científicas
Título:
FPGA IMPLEMENTATION OF A PHASE LOCKED LOOP BASED ON RANDOM SAMPLING
Autor/es:
SONNAILLON, MAXIMILIANO; BONETTO, FABIAN
Reunión:
Conferencia; SPL 2007; 2007
Resumen:
A Phase
Locked Loop (PLL) based on digital signal
processing
and random sampling is proposed in this paper.
Field
Programmable Gate Array (FPGA) technology is used
to
implement a prototype. The random sampling scheme is
used to
reduce the sampling frequency requirements
without
aliasing effects. The possibility of sampling and
processing
at lower frequencies allows the implementation
of
complete-digital high-frequency systems, without
limitations
imposed by the analog to digital converter and
the signal
processing unit. The basic principles are
presented,
and the implemented algorithms are described.
Experimental
results show the PLL performance.