Comparative Study of CNT, Silicon Nanowire & Fullerene embedded multilayer high-k gate dielectric MOS memory devices.

AMRETASHIS SENGUPTA; CHANDAN KUMAR SARKAR; FELIX G. REQUEJO

J. Phys. D: Appl. Phys.

IOP

Año: 2011 vol. 44 p. 405101 - 405113

0022-3727

Here, we present a comparative theoretical study on stacked (multilayer) gate dielectric MOS memory devices, having a metallic/semiconducting carbon nanotube (CNT), silicon nanowire (Si NW) and fullerene (C60) embedded nitride layer acting as a floating gate. Two types of devices, one with HfO2–SiO2 stack (stack-1) and the other with La2O3–SiO2 stack (stack-2) as the tunnel oxide were compared. We evaluated the effective barrier height, the dielectric constant and the effective electron mobility in the composite gate dielectric with the Maxwell–Garnett effective medium theory. Thereafter applying the WKB approximation, we simulated the Fowler–Nordheim (F–N) tunnelling/writing current and the direct tunnelling/leakage current in these devices. We evaluated the I–V characteristics, the charge decay and also the impact of CNT/Si NW aspect ratio and the volume fraction on the effective barrier height and the write voltage, respectively. We also simulated the write time, retention time and the erase time of these MOS devices. Based on the simulation results, it was concluded that the metallic CNT embedded stack-1 device offered the best performance in terms of higher F–N tunnelling current, lower direct tunnelling current and lesser write voltage and write time compared with the other devices. In case of direct tunnelling leakage and retention time it was found that the met CNT embedded stack-2 device showed better characteristics. For erasing, however, the C60 embedded stack-1 device showed the smallest erase time. When compared with earlier reports, it was seen that CNT, C60 and Si NW embedded devices all performed better than nanocrystalline Si embedded MOS non-volatile memories.