Hardware implementation of improved processing architectures for complementary sets of four sequences

PATRICIO DONATO,; FUNES, M. A.; DANIEL CARRICA,; MATÍAS HADDAD,

Santa Fé

Congreso; 9th Argentine Symposium on Computing Technology (AST), 37 JAIIO; 2008

SADIO

Complementary sets of sequences are currently being applied to multiple fields of engineering. Their particular mathematical properties make them very useful in a wide range of aplications (communications, robotics, etc) and allow to implement them in programmable logic devices (e.g. FPGA). Efficient architectures that reduce the computational load has been used in the most of the applications proposed in the literature. This paper describes improved generator and correlator architectures for complementary sets of four sequences, in order to obtain lower hardware requirements for their implementation in FPGAs.