INVESTIGADORES
FUNES Marcos Alan
congresos y reuniones científicas
Título:
Floating Point Multipliers with Reduced FPGA Area
Autor/es:
FUNES, MARCOS; CARRICA, DANIEL; BENEDETTI, MARIO
Lugar:
Mar del Plata
Reunión:
Conferencia; II Southern Conference on Programmable Logic; 2006
Institución organizadora:
ANPCYT-CAECE-UAM
Resumen:
FPGA based Floating Point Multipliers demand abundant logical resources. This paper presents a sequential structure of floating-point multiplier requiring a reduced number of resources. The proposed architecture was evaluated theorically and experimentally achieving a substantially good performance.
