Radiation Damage Characterization of Digital Integrated Circuits

S. SONDÓN; F. PALUMBO; P. MANDOLESI; M. ALURRALDE; P. JULIÁN; A. FILEVICH

Brasil

Workshop; IEEE 10th Latin American Test Workshop; 2009

IEEE

A set of gates and registers was fabricated on a sub-micron CMOS process using radiation hardening by design techniques. The circuits were irradiated in a TANDEM accelerator with 10 MeV protons on three different doses. Off-line characterization of devices was carried out. Measurements showed minimum shifts on the electrical parameters of transistors. Noise margins and gain of combinational logic gates were unchanged and no increase on leakage current was observed. This work suggests that considerable tolerance to this kind of radiation damage can be reached when accurate design techniques are used together with modern integrated circuits technologies.