IIIE 20352
INSTITUTO DE INVESTIGACIONES EN INGENIERIA ELECTRICA "ALFREDO DESAGES"
Unidad Ejecutora - UE
congresos y reuniones científicas
Título:
Verification and Testing of a Piecewise-Linear ASIC Microprocessor Architecture
Autor/es:
RODRIGUEZ J., JULIAN PEDRO, LIPCHITZ OMAR, AGAMENNONI OSVALDO AND JIMENEZ FERNANDEZ VICTOR
Lugar:
Puebla, México
Reunión:
Workshop; Iberchip 08; 2008
Institución organizadora:
Red Iberoamericana de Servicios de Fabricacion de Microsistemas para Soporte a la Industria y Formación de Expertos en Microelectrónica
Resumen:
In this paper, we present validation and testing results of an ASIC that implements a piecewise linear (PWL) architecture. Methodologies for power consumption and maximum operation frequency estimation, based on laboratory measurements, are described. A specification for a debug package feature, which was introduced into the PWL design for proper
silicon validation, is also explained.
