A Digital PLL Circuit for AC Power Lines with Instantaneous Sine and Cosine Computation

R. CAYSSIALS; O. ALIMENTI; E. FERRO

Bariloche, Argentina

Conferencia; IV IEEE Shouthern Conference on Programmable Logic; 2008

In this paper we propose a digital architecture to implement a PLL for a sinusoidal analog input. This kind of components is intended for synchronization between the voltage (current) of a AC power line and a voltage (current) synthesized by a converter. The architecture is based on binary-rate multiplers modules and generates the sine and the cosine values of the sinusoidal input reference. Most of PLLs implemented for those applications utilise analog components whose performance are mainly limited by power supply noise coupling. Besides, they requiere calibrations to avoid precision errors. Our approach proposes a fully digital implementation of a PLL and consequently it is immune to most of the interferences and calibrating errors of analog PLLs. Experimental and theoretical results conclude that the architecture proposed could be suitable for most of the applications where this kind of PLLs is applied.