INVESTIGADORES
JULIAN Pedro Marcelo
artículos
Título:
A Verilog HDL digital architecture for delay calculation
Autor/es:
A. CHACÓN-RODRIGUEZ, F. MARTIN-PIRCHIO, P. JULIÁN, P. S. MANDOLESI
Revista:
LATIN AMERICAN APPLIED RESEARCH
Editorial:
EDIUNS
Referencias:
Lugar: Bahía Blanca; Año: 2007 vol. 37 p. 41 - 45
ISSN:
0327-0793
Resumen:
A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx® FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations.
