SCVDP: A Simplicial CNN Digital Visual Processor

M. DI FEDERICO, P. JULIAN, P. MANDOLESI

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Año: 2014

1057-7122

In this work we present a programmable and reconfigurable single instruction multiple data (SIMD) visual processor based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance low-level image processing. The cells in the array have a selectable neighborhood configuration and several registers, which provide the chip with extended spatial and temporal processing capabilities, in particular optical flow. A prototype 64 $ imes$ 64 cell chip with two program memories and a column adder was fabricated in a 90 nm technology, which running at 133 MHz delivers 102 GOPS. The calculation at the cell level is performed with time coded signals and the program memory is located outside the array. This produces a very efficient realization in terms of area: 39.9 GOPS per mmsuperscript{2}, which is greater than the best result reported so far, even after normalization to account for technology scaling. Computation performance to power ratio of the processor also exceeds all previous results with 790 GOPS/W. Experimental results of the working chip are reported.