FPGA implementation of a low complexity decoder for LDPC codes over impulsive noise channels

ARNONE, L. J.; GAYOSO, A.; GONZALEZ, C. M.; RABINI, M.; CASTIÑEIRA MOREIRA, J.

Buenos Aires

Congreso; Congreso Argentino de Sistemas Embebidos ? CASE 2017; 2017

ACSE

A simplified algorithm for decoding error correcting Low Density Parity Check (LDPC) codes is implemented. The performance of the implemented decoder is studied under the effect of the Additive White Gaussian Noise(AWGN), the Rayleigh fading and the Middleton Class A noise channels. The problem of the distortion and Bit Error Rate (BER) performance degradation produced by impulsive noise leads to modifications in the initialization step of the iterative decoding algorithms for decoding LDPC codes, and this initialization results into increased complexity. This problem is sorted out by simply using an Euclidean distance metric decoder together with a signal amplitude limiter, which allows the use of a simple initialization step. The proposed decoder does not require knowledge of the signal-to-noise ratio of the received signal. Ituses only additions and subtractions, avoiding the use of quotients and products. The algorithm can be easily implemented on programmable logic technology such as Field Programmable Gate Array (FPGA) devices with an excellent BER performance.