INVESTIGADORES
CASTIÑEIRA MOREIRA Jorge
congresos y reuniones científicas
Título:
SUM-SUBTRACT FIXED POINT LDPC LOGARITHMIC DECODER
Autor/es:
ARNONE, L. J.; GAYOSO, A.; GONZALEZ, C. M.; CASTIÑEIRA MOREIRA, J.
Lugar:
Universidad Nacional de Río Cuarto
Reunión:
Congreso; XI RPIC; 2005
Institución organizadora:
Universidad Nacional de Río Cuarto
Resumen:
In this paper a low complexity logarithmic decoder for a LDPC code is presented.The performance of this decoding algorithm is similar to the original decoding algorithm´s, introduced by D. J. C. MacKay and R. M. Neal. It is a simplified algorithm that can be easilyimplemented on programmable logic technology such as FPGA devices because of its use of onlyadditions and subtractions, avoiding the use of quotients and products, and of float point arithmetic.The algorithm yields a very low complexity programmable logic implementation of a LDPCdecoder with an excellent BER performance.
