INVESTIGADORES
MAYA Juan Augusto
congresos y reuniones científicas
Título:
A High Data Rate BPSK Implementation in FPGA for High Dynamics Applications.
Autor/es:
JUAN AUGUSTO MAYA; NICOLÁS ANDRÉS CASCO; JAVIER G. GARCÍA; PEDRO AGUSTÍN RONCAGLIOLO
Lugar:
Córdoba
Reunión:
Conferencia; 2011 VII Southern Conference on Programmable Logic (SPL); 2011
Institución organizadora:
Universidad Nacional de Córdoba
Resumen:
In this paper we present the implementation of a FPGA based high data rate BPSK receiver specifically designed to withstand the high dynamics of airborne vehicles (i.e. aircraft, sounding rockets, satellites, etc.). The carrier recovery is implemented through a Costas loop, and a Gardner detector is used for the timing recovery. This architecture was chosen because it provides almost independent carrier and bit synchronization. Loop filters were designed through analog to discrete-time conversion. A theoretical analysis of the design, simulation and its implementation is presented.
