High-Speed Textural Image Features Extraction using FPGA

GAIA AMOROS, JEREMIAS; TRABES, EMANUEL; OROSCO, EUGENIO CONRADO; ROSSOMANDO, FRANCISCO; SORIA, CARLOS MIGUEL

San Luis

Conferencia; XI Southern Programmable Logic Conference; 2023

Universidad Nacional de San Luis

Computer vision algorithms are present in almost all robotics applications. High-level image operations like image classification, object tracking and pattern recognition need low-level information  about the image texture to work. However, in order to include this compute-intensive tasks in a control loop, they must be executed in the shortest time possible. This article describes a high-speed embedded system to compute different texture-related image features. The system was tested for different image sizes in two Xilinx FPGA platforms: an Alveo U200 Data Center Accelerator Card and a Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. Results are evaluated in comparison to a desktop PC's performance.