Fast and Efficient FPGA Implementation of Polar Codes and SoC Test Bench

KRASSER, F.; LIBERAORI, M. C.; COPPOLILLO, L.; ARNONE, L. J.; CASTIÑEIRA MOREIRA, J.

MICROPROCESSORS AND MICROSYSTEMS

ELSEVIER SCIENCE BV

Lugar: Amsterdam; Año: 2021 vol. 84

0141-9331

In this paper we describe a novel and efficient System on Chip Field Programmable Gate Array (SoCFPGA) implementation and test bench for short Polar Codes on an Intel DE10-Standard DevelopmentKit. Encoder and decoder are synthesized on the FPGA fabric and the whole functionality ofa complete test bench is developed with an embedded ARM-based hard processor system. A VeryHigh Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) parametric designallows synthesis for different code lengths and is suitable for rate-adaptive decoding schemes. We implementfully-unrolled encoder and decoder architectures to achieve high troughputs and lower energyrequirements, and achieve an 11% higher throughput than a reference implementation, for short PolarCodes. A novel Merged Processing Element (MPE) is optimized to be used with Sign-MagnitudeLLR (SM LLR) discrete representations and pre-computing results in the decoder to reduce latencyand resource consumption in comparison to reference designs. A simplified version of this MPE isalso implemented, trading higher latencies for lower resource requirements. The SoC test bench designallows single-board automated testing and is also suitable for other error-correcting schemes.Error-correcting performance is evaluated for different combinations of integer and decimal part bitsin LLR quantified representations. Also a new simplified non-statistical LLR metric was tested withpromising results.