INVESTIGADORES
CASTIÑEIRA MOREIRA Jorge
artículos
Título:
SUM-SUBTRACT FIXED POINT LDPC DECODER
Autor/es:
ARNONE, L. J.; GAYOSO, A.; GONZALEZ, C. M.; CASTIÑEIRA MOREIRA, J.
Revista:
LATIN AMERICAN APPLIED RESEARCH
Editorial:
LATIN AMERICAN APPLIED RESEARCH
Referencias:
Lugar: Bahia Blanca; Año: 2007 vol. 37 p. 17 - 20
ISSN:
0327-0793
Resumen:
In this paper a low complexity logarithmicdecoder for a LDPC code is presented. Theperformance of this decoding algorithm is similar tothe original decoding algorithm´s, introduced by D.J. C. MacKay and R. M. Neal. It is a simplified algorithmthat can be easily implemented on programmablelogic technology such as FPGA devices becauseof its use of only additions and subtractions,avoiding the use of quotients and products, and offloat point arithmetic. The algorithm yields a verylow complexity programmable logic implementationof a LDPC decoder with an excellent BER performance.
