A LDPC LOGARITHMIC DECODER IMPLEMENTATION

ARNONE, L. J.; GAYOSO, A.; GONZALEZ, C. M.; CASTIÑEIRA MOREIRA, J.

PROCEEDINGS VII ISCTA

HW COMMUNICATIONS LTD.

Lugar: Amblside, UK; Año: 2005 vol. 1 p. 356 - 361

<!-- /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-parent:""; margin:0cm; margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:12.0pt; font-family:"Times New Roman"; mso-fareast-font-family:"Times New Roman";} @page Section1 {size:595.3pt 841.9pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:35.4pt; mso-footer-margin:35.4pt; mso-paper-source:0;} div.Section1 {page:Section1;} --> In this paper a logarithmic decoder for a LDPC code is presented. This decoding algorithm performs equally better than the original decoding algorithm introduced by D. J. C. MacKay and R. M. Neal, reducing highly the complexity and overflow and underflow effects of the iterative procedure. It is also a simplified algorithm that can be easily implemented in programmable logic technology like FPGA because it makes use of only additions and subtractions, avoiding the use of quotients and products, and float point arithmetic. The effect of the lookup table that takes into account a correction factor needed for the implementation of the logarithmic form of the algorithm is also analysed. There is no degradation in BER performance for lookup tables of a reasonable size. The decoding algorithm is implemented by utilising only additions and subtractions, and two lookup tables.