Digital Audio Equalizer Implementation using an FPGA with FIR filter bank structure and 4-level PWM-based output DAC Topology

FRANCISCO TOGNI; FACUNDO AGUILERA; GUILLERMO A. MAGALLÁN

Ciudad Autónoma de Buenos Aires

Congreso; 28º Congreso Argentino de Control de Automático; 2023

Asociación Argentina de Control Automático

Abstract—This paper presents the implementation of an audio graphic equalizer based on symmetrical systolic FIR filters. In addition, conversion techniques between analog and digital domains are proposed, using two approaches: 1) active rectification and parallel sampling of analog signal phase and counterphase, and 2) an improved method of differential DAC conversion using PWM signals. Experimental prototype results are obtained in order to validate the proposal and show the performance.