Software PLL based on Random Sampling

M.O. SONNAILLON; RAÚL URTEAGA; FABIÁN J. BONETTO

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Año: 2010 vol. 59 p. 2621 - 2629

0018-9456

This paper presents and analyzes a phase-lockedloop (PLL) based on digital signal processing (DSP) and randomsampling (RS). Traditional DSP techniques based on uniformsampling require sampling at more than twice the PLLfrequency to avoid spectrum aliasing. This requirement makesdifficult the implementation of high-frequency software-basedPLLs. RS techniques allow significantly reducing the samplingspeed requirements without aliasing effects. Lower speed requirementsin the analog-to-digital converter (ADC) and the processingdevice enable the implementation of software PLLs for muchhigher frequencies than traditional techniques. The proposedPLL is mathematically analyzed to describe its operation andcharacterize its performance. A field-programmable gate array(FPGA)-based PLL prototype is presented to validate the theoreticalanalysis.