Evaluation of MOSFET parallelization performance: power losses and thermal performance for H-bridge power converter modules

GARCIA RETEGUI, R.A.; PITTET, S.; WASSINGER, N.; BURNET, J.P.; MAESTRI, S.; UICICH, G.

2018-12-20/2019-07-25

1-37

Electrónica

Energia-Electrica

The aim of this report is to compare the performance of different MOSFETs regarding the associated power losses and thermal behavior, since they represent a substantial amount of the converter power losses. The performance of several MOSFETs that form each module is evaluated, including thermal response and power losses. In this sense, the MOSFET selection is based on covering a range in blocking voltage and maximum current, together with different packages. With respect to the thermal response, the packages under analysis allow heat evacuation through pcb or directly to a coldplate, which implies different thermal models. For the particular case of evacuation through pcb, the thermal model is obtained when the thermal vias are only below the device thermal pad. Moreover, due to the small packages used, an expansion beyond thermal tab is analyzed. On the other hand, some features associated to the pcb, like number of layers and thickness are analyzed. Thus, thermal models for each package are obtained. The power losses calculation includes power losses associated to commutation, conduction, reverse recovery, diode conduction and drivers; considering synchronous rectifier operation. Simulation results are presented, considering different implementations of parallel switches, number of modules and switching frequency. In this context, thermal viable cases are defined as those that present both junction temperature and pcb temperature below certain thresholds.The amount informed in the technical report accounts for the second payment that corresponds to the 30% of the first stage in the R & D agreement "Study of Power Converter Topologies suitable for HL-LHC Inner Triplet magnets with Energy Recovery".