INSTITUTO DE INVESTIGACIONES CIENTIFICAS Y TECNOLOGICAS EN ELECTRONICA
Unidad Ejecutora - UE
congresos y reuniones científicas
FPGA implementation of a low complexity decoder for LDPC codes over impulsive noise channels.
GONZÁLES CLAUDIO; GAYOSO CARLOS; CASTIÑEIRA MOREIRA JORGE; ARNONE LEONARDO; RABINI MIGUEL
Congreso; Congreso Argentino de Sistemas Embebidos 2017; 2017
Sociedad Argentina de Sistemas Embebidos. UBA
A simplified algorithm for decodingerror-correcting Low Density Parity Check (LDPC) codes isimplemented. The performance of the implemented decoder is studied under theeffect of the Additive White Gaussian Noise (AWGN), the Rayleigh fading and theMiddleton?s Class A noise channels. The problem of the distortion and Bit ErrorRate (BER) performance degradation produced by impulsive noise leads tomodifications in the initialization step of the iterative decoding algorithmsfor decoding LDPC codes, and this initialization results into increasedcomplexity. This problem is sorted out by simply using an Euclidean distancemetric decoder together with a signal amplitude limiter, which allows the useof a simple initialization step. The proposed decoder does not requireknowledge of the signal-to-noise ratio of the received signal. It uses onlyadditions and subtractions, avoiding the use of quotients and products. The algorithmcan be easily implemented on programmable logic technology such as FieldProgrammable Gate Array (FPGA) devices with an excellent BER performance.