Fast and efficient FPGA implementation of Polar Codes and SoC test bench

MÓNICA LIBERATORI; JORGE CASTIÑEIRA MOREIRA; LEONARDO COPPOLILLO; FEDERICO KRASSER; LEONARDO ARNONE

MICROPROCESSORS AND MICROSYSTEMS

ELSEVIER SCIENCE BV

Lugar: Amsterdam; Año: 2021 vol. 84

0141-9331

In this paper we describe a novel and efficient System on Chip Field Programmable Gate Array (SoC FPGA) implementation and test bench for short Polar Codes on an Intel DE10-Standard Development Kit. Encoder and decoder are synthesized on the FPGA fabric and the whole functionality of a complete test bench is developed with an embedded ARM-based hard processor system. A Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) parametric design allows synthesis for different code lengths and is suitable for rate-adaptive decoding schemes. We implement fully-unrolled encoder and decoder architectures to achieve high troughputs and lower energy requirements, and achieve an 11% higher throughput than a reference implementation, for short Polar Codes. A novel Merged Processing Element (MPE) is optimized to be used with Sign?Magnitude LLR (SM LLR) discrete representations and pre-computing results in the decoder to reduce latency and resource consumption in comparison to reference designs. A simplified version of this MPE is also implemented, trading higher latencies for lower resource requirements. The SoC test bench design allows single-board automated testing and is also suitable for other error-correcting schemes. Error-correcting performance is evaluated for different combinations of integer and decimal part bits in LLR quantified representations. Also a new simplified non-statistical LLR metric was tested with promising results.