Hybrid Sort Algorithm Implemented by High Level Synthesis

M. ANTONELLI; M. L. ACOSTA; L. DE MICCO

IEEE LATIN AMERICA TRANSACTIONS

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Lugar: New York; Año: 2019 vol. 18 p. 430 - 437

1548-0992

This paper proposes a hybrid data ordering algorithm which executes serial and parallel instructions. The implementation of the system is presented in the Zedboard development board of Xilinx that includes a SoC (System on Chip).The design was done in high level language HLS (High Level Synthesis). It receives a vector of N elements and delivers the set of indexes of the L major elements ordered. The complexity of the algorithm is analyzed in a generic way. The required times and resources are