IDIT   25587
INSTITUTO DE ESTUDIOS AVANZADOS EN INGENIERIA Y TECNOLOGIA
Unidad Ejecutora - UE
congresos y reuniones científicas
Título:
An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
Autor/es:
ARIEL L. POLA; BENJAMIN T. REYES; RAUL SANCHEZ; MARIO R. HUEDA
Lugar:
Florianopolis
Reunión:
Conferencia; 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS); 2016
Resumen:
This work describes a 1 Gb/s digital communication system implemented on an FPGA-based platform to investigate mixed-signal calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs). Design of multi-gigabit TI-ADCs is of great interest for next generation digital communication systems such as optical coherent networks.In these applications, mismatches of the sampling time, gain, offset, and frequency response among the interleaves of a TI-ADC limit the performance of the converter unless they are compensated. Typically, long computer simulation run time is required to evaluate the performance of mixed-signal calibration algorithms. We show that the FPGA-based system described in this paper drastically reduces the emulation time by more than hundreds of magnitude orders. The proposed FPGA framework includes: (i) a diagnostic and control unit built upon an embedded processor NIOSII, (ii) DSP blocks to implementthe transmitter and the receiver, and (iii) a Gaussian number generator to emulate the noise channel component. Experimental results with a 2 GS/s 6-bit CMOS TI-ADC demonstrate the excellent capability of the implemented FPGA-based emulator to evaluate the performance of a mixed-signal calibration algorithm.
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