Breaking the barriers to advanced power management in systems on a chip

CARLUCHO R.; ROSSI S. R.; TODOROVICH E.; BRINKS R.; PAOLETTI G.

Buenos Aires

Simposio; 2016 Seventh Argentine Symposium and Conference on Embedded Systems (CASE); 2016

IEEE

Complexity in System on a Chip (SoC) design is rapidly escalating with the advent of more advanced nodes and the ability to integrate 100?s of cores on a single die. This highlights the need to understand the power consumption of the device in the early architectural phases of SoC design. The Power Analysis tooling, centered on Network on a chip, and developed as part of this project allows for quick iteration of power management topologies and tradeoffs in power managementpolicies. The approach followed allows for successive iteration and composability of the solution as the design progresses and additional details become available. Flexibility is present in the system to assign both degree of uncertainty and replace the imprecise information with new information as the design process is completed.