Parallelism analysis for a multi-core speech recognition architecture

A. PASCIARONI, P. JULIAN; A. G. ANDREOU

Mar del Plata

Congreso; Argentine Conference on Electrronics; 2019

Universidad Nacional de Mar del Plata

In this work, we present an analysis of data parallelismfor a multiple core chip. The aim of this work isto optimally utilize different levels of spatial parallelism asa strategy to reduce the energy consumption of the wholearchitecture. The core in the analysis implements a GaussianMixture Model for automatic speech recognition. In the firstplace, we analyze the optimal degree of parallelism at the microarchitecturelevel. In the second place, we analyze the parallelismat the multiple core level and perform an optimization thatminimizes the energy-delay product of the whole system. Allanalysis are performed using simulation data from synthesis ina 55nm CMOS technology.