All-Digital High-Resolution PWM With a Wide Duty-Cycle Range

PABLO S. MANDOLESI; FERNANDO CHIERCHIE; JUAN I. MORALES; EDUARDO E. PAOLINI

Mar del Plata, Buenos Aires

Congreso; 2019 Argentine Conference on Electronics (CAE); 2019

Universidad Nacional de Mar del Plata

An all-digital high-resolution pulse-width modulator in standard 130-nm CMOS technology is presented in this work. The architecture is based on a digitally-controlled delay element with variable time interval up to 50 ps and adjustable against process, voltage and temperature (PVT) variations. Post-layout simulation results show a linear response between the control word and delay. The PWM modulator uses several delay elements in a hybrid configuration that allows to obtain duty cycles with 18-bit resolution, without using a high-frequency internal clock while maintaining low power consumption.