IIIE 20352
INSTITUTO DE INVESTIGACIONES EN INGENIERIA ELECTRICA "ALFREDO DESAGES"
Unidad Ejecutora - UE
congresos y reuniones científicas
Título:
Verification and Testing of a Piecewise-Linear ASIC Microprocessor Architecture
Autor/es:
O. LIFSCHITZ, J. A. RODRIGUEZ, P. JULIÁN, O. AGAMENNONI, V. M. JIMÉNEZ-FERNANDEZ
Lugar:
Buenos Aires, Argentina
Reunión:
Workshop; XV IBERCHIP; 2009
Institución organizadora:
IBERCHIP
Resumen:
In this paper, we present validation and testing results of an ASIC that implements a piecewise linear (PWL) function computing architecture. Methodologies for power consumption and maximum operation frequency estimation, based on laboratory measurements, are described. A specification for a debug package feature, which was introduced into the ASIC design for proper silicon validation, is also explained.
