PWL cores for nonlinear array processing

DI FEDERICO, MARTIN; JULIAN, PEDRO; MANDOLESI, PABLO S.; ANDREOU, ANDREAS G.

Paris, Francia

Simposio; Circuits and Systems (ISCAS); 2010

Sociedad de Circuitos y Sistemas de lEEE

This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized. Based on a 90nm technology process, the different options will be analyzed and compared using simulations.