Highly configurable Ethernet controller for HW/SW co-debugging

LORENZO DE PASQUALE; DAMIÁN BANFI; E. FERRO; R. CAYSSIALS; DIEGO MARTINEZ

Buenos Aires

Congreso; Congreso Argentino de Sistemas Embebidos; 2017

SASE

FPGA devices allows designer to implement complex digital architectures that involve hardware and software components. Because of the different features of hardware and software design, diverse mechanisms and tools have been proposed for debugging and verification of architectures implemented on FPGA devices. Bus level transactions and data processing algorithms are usually difficult to manage together because differences between the inspection times involved. While hardware transactions are related to system clock periods, data processing algorithms are related to software execution times. In this paper, an Ethernet controller is proposed as a low invasive component to extract runtime hardware and software information for system debugging and verification. The information produced may be analyzed to locate hardware and software failures as well as to improve the system performance tuning its configuration parameters. A case study is proposed as a real application.