IIIE   20352
INSTITUTO DE INVESTIGACIONES EN INGENIERIA ELECTRICA "ALFREDO DESAGES"
Unidad Ejecutora - UE
congresos y reuniones científicas
Título:
Functional verification of FFT cores
Autor/es:
GABRIEL PACHIANA CABA; JUAN AGUSTÍN RODRIGUEZ; EDUARDO E. PAOLINI
Lugar:
Mendoza
Reunión:
Conferencia; Conferencia de la 2014 Argentine School of micro-nanoelectronics, technology and applications; 2014
Institución organizadora:
Universidad Tecnológica Nacional Facultad Regional Mendoza
Resumen:
This paper presents an initial approach to the development of a component for black box functional verification of FFT cores. First, a coverage model based on equivalence partitioning and boundary value analysis of the input signal space is defined, allowing to identify a set of test cases of interest. Then, the design and implementation of a SystemVerilog testbench is described and employed to stimulate three FFT IPs, performing a coverage driven verification procedure for checking performance, configurations and accuracy correctness