Efficient Decision FeedForward Equalizer with Parallelizable Architecture

A. POLA; J. E. COUSSEAU; O. AGAZZI; M. HUEDA

Beijing

Congreso; 2013 IEEE International Symposium on Circuits and Systems; 2013

Institute of Electrical and Electronic Engineering

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers operating on highly dispersive channels. The DFFE has been recently proposed for multigigabit communication receivers, where the use of parallel processing is required. Well-known parallel architectures for the traditional decision feedback equalizer (DFE) have a complexity which grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to iteratively cancel intersymbol interference (ISI). Additional complexity reduction can be achieved by improving the reliability of the initial tentative decisions. To provide more reliable initial tentative decisions to the DFFE, a simple reduced-state Viterbi algorithm (VA) is proposed in this work. Computer simulations demonstrate that the combination of DFFE and VA not only allows a similar performance to the typical DFE to be achieved, but it also results in a significant complexity reduction.