IIIE 20352
INSTITUTO DE INVESTIGACIONES EN INGENIERIA ELECTRICA "ALFREDO DESAGES"
Unidad Ejecutora - UE
congresos y reuniones científicas
Título:
A Generic Nonlinear Output Error Structure Implemented on a PWL ASIC
Autor/es:
LIFSCHITZ OMAR; AGAMENNONI OSVALDO
Lugar:
Córdoba
Reunión:
Seminario; 2012 Argentine School of Micro-Nanoelectronics, Technology and Applications; 2012
Institución organizadora:
Universidad Católica de Córdoba
Resumen:
In this paper, we present a Nonlinear Output Error (NOE) model structure implemented on an Application Specific Integrated Circuit (ASIC) chip dedicated to Piecewise Linear (PWL) calculation. Three examples are included to show the performance of the ASIC in quantization, truncation and fixedpoint operation. Experimental results and simulation results are shown and compared.
